Designers of memory circuits have moved to gate dielectric materials having a high dielectric constant, e.g., metals such as hafnium, for implementation of gates in metal oxide semiconductor (MOS) transistors. As transistor dimensions decrease, gate resistance becomes a challenge. For example, gate resistance is higher, e.g., by almost a factor of three, in 20 nm nodes relative to 28 nm nodes. Such increased gate resistance is due to a reduced channel length, which may be, e.g., 18 nm. Wide oxide definition (OD) transistors experience increased gate delay due to such increased resistance, because gate delay is proportional to resistance. Oxide definition refers to definition of diffusion areas such as source, drain and interconnect.
Increased gate delay causes slower timing performance in circuitry, e.g., word line drivers in static random access memory (SRAM) memory circuits. A word line driver, which may be an inverter circuit, may have a high loading, which requires a large physical device. A known word line driver has a short channel length and a relatively wide oxide definition region, which corresponds to a relatively long distance between a gate and a PMOS region of the word line driver. The wide oxide definition region corresponds to a long poly gate, which leads to increased gate resistance, because a large parasitic resistance is formed in the poly gate at the PMOS region and also at an NMOS region of the inverter between a gate region and the PMOS region. As the width of the OD region increases (i.e., as the distance between the gate region and the PMOS region increases in order to support increased loading), gate resistance increases, slowing circuit performance.